1. Technical Field
This invention relates to displays, and more particularly to an array substrate and a method of fabricating the array substrate using a low-mask technology.
2. Related Art
LCD devices may be formed on a substrate using photolithography. Photolithography is method that patterns surfaces on a substrate. To create a circuit pattern on a substrate, a pattern is first transferred onto a layer of photoresist overlying a substrate surface. Photoresist is a light sensitive-material similar to a coating on photographic film. Exposure to light through an optical mask causes changes in the photoresist's structure and properties. A second transfer takes place when etchants remove those portions of the substrate's top layer that are not covered by the photoresist.
FIG. 1 is a plan view illustrating a method of fabricating a circuit that may be used in an LCD device. In an active region having n-type TFTs, a unit pixel region is formed by crossing gate lines 12a with data lines 15. An electrode 17 in the unit pixel region applies a signal to a liquid crystal for light transmission and a storage capacitor maintains electric charge when the unit pixel region is not selected.
As shown in FIGS. 1, 2A, 2D, 2F, or 2H the n-type TFT is comprised of a first semiconductor layer 54a having a channel layer, source/drain regions, and a gate insulating layer (‘13’ of FIG. 2F) that overlies the first semiconductor layer 54a and underlies a first gate electrode 12 and an insulating interlayer (‘23’ of FIG. 21). First source/drain electrodes 15a and 15b (FIG. 2D) are in contact with the source/drain regions of the first semiconductor layer 54a through a first contact hole 71 (FIG. 2F) in the insulating interlayer 23. The drain electrode 15b is connected to a pixel electrode 17 through a second contact hole 81 (FIG. 2H) to apply a voltage to the pixel electrode 17.
A storage capacitor may be formed through the second semiconductor layer 54b doped with an impurity. A storage electrode 19 interconnected to the storage capacitor may be formed on the same layer as the gate line 12a with a gate insulating layer 13 interposed there between (FIGS. 1 and 2H). The second semiconductor layer 54b and the storage electrode 19 extended and are biased outside of the active region.
Patterning an image onto a substrate surface is a multi-step process that has been compared to stenciling. In FIG. 2A, the process begins by depositing a buffer layer 52 of insulating material such as silicon oxide SiOx onto an insulating substrate 11. An amorphous silicon layer is then deposited onto the buffer layer 52 and crystallized into a polysilicon layer through an exposure to a laser. The polysilicon layer is then patterned to form first, second, and third semiconductor layers 54a, 54b and 54c. In FIG. 2A, the semiconductor layers 54a, 54b and 54c have island shapes, wherein the first and third semiconductor layers 54a and 54c are n-type TFT and p-type TFT, respectively, and the second semiconductor layer 54b is a storage layer.
In FIG. 2B, a first photoresist 31 is deposited across the entire top surface of the insulating substrate 11, and is then patterned using a second mask to cover the entire first semiconductor layer 54a of the n-type TFT region and the entire third semiconductor layer 54c of the p-type TFT region. A storage doping process is applied across the entire surface of the insulating substrate 11, to dope the second semiconductor layer 54b with an impurity.
As shown in FIG. 2C, an inorganic material is then deposited across the entire upper surface of the insulating substrate 11 by a PECVD process (Plasma Enhanced Chemical Vapor Deposition), to form a gate insulating layer 13. A low-resistance metal layer is then deposited on the gate insulating layer 13. The metal layer is positioned above the semiconductor layers 54a, 54b and 54c. 
In FIG. 2C, the first and second gate electrodes 12 and 22 and a storage electrode 19 are patterned above the metal layer through photolithography. At this stage, the first and second gate electrodes 12 and 22 extend in different directions from the gate line 12a (of FIG. 1). The storage electrode 19 is formed in parallel with the gate line 12a, and is positioned above the second semiconductor layer 54b of the storage region to form a storage capacitor.
In FIG. 2D, the entire surface of the insulating substrate 11 is then lightly doped with an n-type impurity in which the first and second gate electrodes 12 and 22 and the storage electrode 19 are used as masks. This process forms LDD (lightly doped drain) doping layers 88 at both sides of the first and second gate electrodes 12 and 22. In FIGS. 2D and 2G, portions of the insulating substrate 11 undoped with the n-type impurity ions act as the first and second channel layers 14 and 24, whereby the LDD doping layer 88 may be controlled by an electric field in a contact region.
In FIG. 2D, a second photoresist 33 is then deposited on the entire surface of the insulating substrate 11 including the first gate electrode 12, the p-type TFT region, and the storage region leaving the first semiconductor layer 54a of the n-type TFT region exposed. As shown, the second photoresist 33 entirely covers the gate electrode 12 of the n-type TFT region. The entire surface of the insulating substrate 11 is then heavily doped with n-type impurity ions to form the first source/drain regions 15a and 15b in the first semiconductor layer 54a of the n-type TFT region.
After the second photoresist 33 is removed, a third photoresist 35 is deposited onto the entire surface of the insulating substrate 11 as shown in FIG. 2E. The third photoresist 35 is then patterned to cover the first gate electrode 12 and the storage electrode 19 while exposing the third semiconductor layer 54c of the p-type TFT region. With a portion of the upper surfaces masked, the entire surface of the insulating substrate 11 is heavily doped with p-type impurity ions to form second source/drain regions 25a and 25b in the third semiconductor layer 54c. 
With the removal of the third photoresist 35 in FIG. 2F, an insulating material is deposited across the entire surface of the insulating substrate 11 through a PECVD process. A first contact hole 71 is then formed through the gate insulating layer 13 and the insulating interlayer 23 to expose portions of the first and second source/drain regions 15a, 15b, 25a and 25b. The first contact hole 71 may be formed by selectively removing portions of the gate insulating layer 13 and the insulating interlayer 23 through photolithography.
In FIG. 2G, first and second source/drain electrodes 15c, 15d, 25c and 25d are respectively connected to the first and second source/drain regions 15a, 15b, 25a and 25b through the first contact hole 71 to form the CMOS-TFT having an n-type TFT and a p-type TFT. As shown, a low-resistance metal layer is passed through the contact hole 71 and is contoured to an inner circumference of the contact hole 71 and the undulating upper surfaces of the insulating layer 23. The low resistance metal layer is patterned by photolithography. The first and second source electrodes 15c and 25c extend away from the data line (‘15’ of FIG. 1).
In FIG. 2G, the n-type TFT including the first gate electrode 12, the first source/drain electrodes 15c and 15d, and the first channel layer 14 are formed in each pixel region and the p-type TFT including the second gate electrode 22, the second source/drain electrodes 25c and 25d, and the second channel layer 24 is formed in the driving circuit region. The pixel region also includes the second semiconductor layer 54b, the gate insulating layer 13, and the storage electrode 19.
In FIG. 2H, an inorganic or organic insulating material is deposited on the entire surface of the insulating substrate 11 including the first source/drain electrodes 15c and 15d to form a passivation layer 16. The passivation layer 16 and the insulating interlayer 23 (FIGS. 2G and 2H) are then etched to expose the first drain electrode 15d through a second contact hole 81 through photolithography.
In FIG. 2I, ITO (indium-tin-oxide) or IZO (indium-zinc-oxide) is deposited in contact with the first drain electrode 15d through the second contact hole 81, and then patterned through photolithography to form a pixel electrode 17.
In the aforementioned multi-step process for fabricating a CMOS-TFT array substrate, circuits are patterned on the insulating substrate 11 through nine steps. Although other steps are not described, the process may further include bonding the TFTs to an opposing substrate through sealant; positioning spacers between the substrates; interjecting a liquid crystal between the two substrates to form a liquid crystal layer; and then sealing the liquid crystal layer to form the LCD device.
The present invention is directed to a system and method that minimize the number of steps needed to fabricate an array substrate. By minimizing the steps of fabrication, the process minimizes the number of steps that variations and defects may occur.